1. Field of the Invention
The present invention relates to a substrate processing apparatus and a method of processing a substrate, and more particularly, to a substrate processing apparatus and a method of processing a substrate such as a semiconductor wafer.
2. Description of the Related Art
As illustrated in FIGS. 8A and 8B, in general, a substrate processing apparatus includes an outer insulating layer a including a cylindrical wall surface, a reaction container c installed in the outer insulating layer a, a boat d installed in the reaction container c and on which a semiconductor wafer is loaded, and a heater b installed on an inner wall of the outer insulating layer a to heat the inside of the reaction container c.
In order to thermally process the semiconductor wafer in the substrate processing apparatus, the semiconductor wafer at room temperature is loaded in the reaction container c while being placed on the boat d, thermally processed by heating the semiconductor wafer to a predetermined temperature by the heater b, and cooled down to the room temperature, and then the boat d is moved downward.
The shorter a recipe time needed to perform a series of operations described above, the better the productivity of the substrate processing apparatus. To reduce the recipe time, temperature recovery characteristics which are temperature change characteristics when the semiconductor wafer is heated from the room temperature to a target temperature and is cooled from the target temperature to the room temperature are important. To improve the temperature recovery characteristics, a heat radiation property of the heater b should be improved.
FIG. 8A illustrates a substrate processing apparatus including an outer insulating layer a with thin wall surfaces. FIG. 8B illustrates a substrate processing apparatus including an outer insulating layer a with thick wall surfaces. In the substrate processing apparatus including the outer insulating layer a with the thin wall surfaces, a semiconductor wafer is heated to a temperature which is higher than a target temperature but is rapidly cooled to the target temperature as indicated by a solid line A in FIG. 9. In contrast, in the substrate processing apparatus including the outer insulating layer a with the thick wall surfaces, a semiconductor wafer is difficult to be cooled down. Thus, once the semiconductor wafer is heated to a temperature which is higher than the target temperature, the semiconductor wafer is difficult to be rapidly cooled down to the target temperature as indicated by an alternated long and short dash line B in FIG. 9.
However, in the substrate processing apparatus having the thin outer insulating layer a and high heat radiation properties, power consumption increases to compensate for heat radiated via a surface of the outer insulating layer a.
Conventionally, a technique of designing a heater with the outer insulating layer a having a predetermined thickness has been employed in consideration of a balance between the temperature recovery characteristics and power consumption. However, when the technique is employed, high temperature recovery characteristics or low power consumption should be given up or both the temperature recovery characteristics and power consumption should be controlled to an appropriate level. Accordingly, it is impossible to increase the temperature recovery characteristics while reducing power consumption.
To solve this problem, for example, a reaction container 3 is installed in a heater layer 2 including an outer insulating layer 1, a wafer loading means 5 on which a wafer 4 is loaded is inserted into the reaction container 3, an air flow channel 6 is installed between the heater layer 2 and the reaction container 3, a hollow air insulating layer 10 is installed between the outer insulating layer 1 and the heater layer 2 in a vertical diffusion chemical vapor deposition (CVD) furnace connected to an exhaust device 9 that exhausts air in the air flow channel 6 via an in-heater heat exhaust gate 7 and a radiator 8, and a heat exhaust gate 12 is installed at an air emission side of the hollow air insulating layer 10 communicating with the radiator 8 (see patent document 1).